基于拼接缝自适应消除和全景图矫直的快速图像拼接算法

针对图像拼接存在色差过渡不均匀、图像倾斜扭曲及拼接效率低的现象，提出一种基于拼接缝自适应消除和全景图矫直的快速图像拼接算法。首先，用尺度不变特征变换（SIFT）提取图像指定区域特征点并用双向K近邻（KNN）算法进行图像配准，有效提高算法效率；其次，利用动态规划思想提出自适应公式找到最优拼接缝并用图像融合算法对其自适应消除，解决拼接缝色差过渡不均匀问题；最后，针对累积拼接误差形成全景图倾斜的现象，利用边缘检测算法提出自适应拟合四边形矫直模型，把原始全景图矫直为一个全新的全景图。所提算法与分块图像拼接和二叉树图像拼接算法相比，图像质量提升了5.84%~7.83%，拼接时间仅为原来的50%~70%。实验结果表明，该算法不仅通过自适应更新机制减少不同图像背景下拼接缝色差过渡不均匀的现象，从而提高了图像质量；而且提高了拼接效率，降低了全景图倾斜扭曲程度。     

优化特征提取的互动式人脸活体检测研究

针对人脸识别系统中出现的通过照片或视频“欺诈”解锁问题，提出一种活体检测方法，通过随机指令判断被检测对象是否为真人。利用HOG特征和随机森林算法对摄像头采集的图像进行人脸检测，预测脸部68个特征点位置，把68个特征点位置和脸部位置的相对位置归一化后作为姿态的特征，提取的姿态特征与SVM分类器相结合，训练出分类效果较好的头部姿态估计分类器。通过多次实验，对特征提取方法进行优化，进一步提高检测准确率。最后，使用随机互动式命令序列对被检测人发出指令，实现活体检测。该方法对头部姿态估计具有较高的鲁棒性，并且可以有效地防范照片和视频认证攻击。     

加权信息熵与增强局部二值模式结合的人脸识别

针对人脸识别因光照、姿态、表情、遮挡及噪声等多种因素的影响而导致的识别率不高的问题，提出一种加权信息熵（IEw）与自适应阈值环形局部二值模式（ATRLBP）算子相结合的人脸识别方法（IE （w） ATR-LBP）。首先，从原始人脸图像分块提取信息熵，得到每个子块的IEw；然后，利用ATRLBP算子分别对每个人脸子块提取特征从而得到概率直方图；最后，将各个块的IEw与概率直方图相乘，再串联成为原始人脸图像最后的特征直方图，并利用支持向量机（SVM）对人脸进行识别。在AR人脸库的表情、光照、遮挡A和遮挡B四个数据集上，IE （w） ATR-LBP方法分别取得了98.37%、94.17%、98.20%和99.34%的识别率。在ORL人脸库上，IE （w） ATR-LBP方法的最大识别率为99.85%；而且在ORL人脸库5次不同训练样本的实验中，与无噪声时相比，加入高斯和椒盐噪声后的平均识别率分别下降了14.04和2.95个百分点。实验结果表明，IE （w） ATR-LBP方法能够有效提高人脸在受光照、姿态、遮挡等影响时的识别率，尤其是存在表情变化及脉冲类噪声干扰时的识别率。     

Reliable techniques for integrated circuit identification and true random number generation using 1.5-transistor flash memory

Flash memory bits, like other integrated circuit (IC) devices, are prone to random variability in their actual versus nominal characteristics. We present the use of 1.5-transistor flash memory cells in physically unclonable functions leveraging their erase speed variability. This type of memory is interesting for the internet of things due to its wide availability as intellectual property at foundries. Using experimentally measured results, we show simple methods that provide high reliability with no or limited need for helper data and error correction. High quality fingerprints for IC identification are demonstrated. Moreover, techniques to remove systematic variations from the array response are shown, allowing the resulting binary strings to pass all National Institute of Standards and Technology tests for randomness. Consequently, with low complexity helper functions, true random numbers can be readily produced.     

STL模型特征信息的自适应分层的研究

模型的分层是3D打印前处理的一个重要环节，针对目前分层算法效率低、不能有效保留模型细微特征的问题，提出了一种新的基于STL模型特征信息的思想。首先提取模型的特征边，对特征边内实体表面采用区域增长算法进行表面分割，然后对分割后的表面判断其类型，最后对于不同的表面类型采用不同的分层求交处理算法。利用VC++6.0平台和OpenGL显示技术，依据模型表面几何特征自适应地变动层厚，减小台阶效应，加快分层效率，同样能很好地保留模型局部特征，且该算法可以根据实际模型的成型方向，实现分层方向的改变，保证成型零件的精度。     

Olfactory appraisal of odorants for 100% hydrogen networks

To meet carbon emissions reduction targets heat and transport need to be decarbonised. Hydrogen is being considered as a flexible energy vector that could play an important part in this endeavour. With demonstration projects on the rise it is crucial to identify suitable odorants to ensure, safety regulations are met and public acceptance gained. Specifically, this work investigates the use of sulphur based odorants currently in use in the UK and Europe, alongside sulphur-free and experimental ones, for use in a 100% hydrogen gas demonstration network in the UK. Gas samples odorised with five different odorants are analysed to determine odour detection threshold, the odour intensity, its hedonic tone and character. The tests are performed by an accredited laboratory following EU standards. The results show that four odorants meet requirements as stenching agents for use in UK gas distribution network, whilst one, 5-ethylidene-2-norbornene, fails to demonstrate an unpleasant odour.     

Towards standardisation of proof load testing: pilot test on viaduct Zijlweg

Proof load tests of bridges can be very useful for structures with a lack of information, or for structures of which the effect of material degradation is difficult to assess. Contrary to diagnostic load testing, proof load testing is not well-defined in current standards in terms of required load and analysis of measurements. The risk related to the high loads used in proof load testing requires standardisation for these tests. The paper highlights important considerations for proof load testing that may lead to the development of guidelines in the Netherlands, by illustrating a pilot study on the viaduct Zijlweg in the Netherlands. This reinforced concrete bridge rates too low in shear. Topics of interest are the required load that the bridge has to withstand to be approved by the load test and the interpretation of the measurements during the test to avoid permanent damage to the structure. These measurements were compared to the stop criteria from existing codes for buildings, to examine if recommendations for the use with bridges can be formulated. The final result of the test on this case study is that the capacity of the viaduct is proven to be sufficient for shear and bending moment.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.